Microsemi Corporation (Nasdaq: MSCC), a leading provider of differentiated semiconductor technology solutions for power, safety, reliability and performance, today announced it is the first supplier of RISC-V A programmable logic device (FPGA) provider that offers a comprehensive software toolchain and intellectual property (IP) core. The RV32IM RISC-V core is suitable for use in the MEGA Sensei IGLOO ™ 2 FPGAs, SmartFusion ™ 2 SoC FPGAs or RTG4 ™ FPGAs, with the Eclipse-based SoftConsole IDE and Libero SoC Design kits to provide comprehensive design support.
The new RV32IM RISC-V core, developed in collaboration with SiFive, enables customers to design with the Open Instruction Set Architecture (ISA), enabling full portability and a more secure processor architecture with licensed BSD licenses. RISC-V is the new ISA, and is now the standard open architecture that RISC-V Foundation oversees. RISC-V offers a compelling software processor solution for MEGA's low-power, reliable, and secure FPGAs. The RV32IM RISC-V core opens up a new generation of innovation for embedded designers. Now, engineers can rely on open ISA, do not need to be subject to a single vendor, and can use open source tools and hardware. Never before has any processor enabled designers to review, modify, rewrite, collaborate on their designs, and migrate their designs to the best platform for their products. With high security, embedded low-power FPGAs are ideal for this new paradigm.
"Our IGLOO2, SmartFusion2 and RTG4 devices are ideal for building RISC-V cores," said Venki Narayanan, senior director of software and systems engineering for SoC's SoC product group. "We reduce power consumption by up to 50 percent and provide customers with IP- Proven security RISC-V is ideally suited for reshaping processor power for security, trust and reliability, which are at the heart of MEGA's solutions, and by further investing in this architecture, To ensure that customers have long-term road map support, thereby continuing to consolidate our leading position in this technology.
Customers looking to develop custom devices can now integrate their designs into MEGA's FPGAs, allowing their solutions to be introduced to market faster. Combined with its Libero SoC design kits, the USGOOM IGLOO2 FPGAs, SmartFusion2 SoC FPGAs, or RTG4 FPGAs combine to create an ideal platform for RISC-V cores for a wide range of embedded applications, and their size and power consumption make them very easy to implement. The US-based Safe Low Power FPGA family provides customers with an effective architecture that protects their IP and ensures long-term support for their designs in the industrial, defense, security and medical markets. The Libero SoC design suite enables designers to implement their designs and efficiently utilize FPGA logic cells (LEs) for a cost-effective solution. The Eclipse-based SoftConsole IDE runs on Linux, enabling users to compile and debug their source code. This IP core and software platform is the first complete RISC-V solution for FPGAs.
Because the register transfer level (RTL) source code is available for inspection, the new RV32IM RISC-V core is ideal for applications such as security and security. For example, customers themselves can verify the security of the processor, which is the use of other closed-architecture processor can not be done. In security-critical applications, customers can run several RISC-V cores, and when one fails, make sure there are redundant cores to take over.
"We are delighted that Microsemi has released the RISC-V intellectual property core for its IGLOO2, SmartFusion2 and RTG4 FPGAs," said Rick O'Connor, executive director of RISC-V Foundation. "The company's comprehensive Linux-based toolchain enables a wide range of customers to "The development of the RISC-V core in MEGA's FPGA devices, and I highly commend MCC for its leadership in rolling out this comprehensive RISC-V platform, and we look forward to working with it to explore future developments."
MEGA's early involvement in the creation of the RISC-V Foundation established leadership in new standards and ecosystems and is now working closely with non-profit organizations to ensure that ISA is the industry standard for a wide range of computing devices. Ted Speers was appointed as the first board member of the RISC-V Foundation in July 2016 and Ted Marena, director of marketing for SoC FPGAs, was recently elected Vice Chairman of the RISC-V Marketing Committee .